1. Field of Invention
The invention relates to a method of forming a semiconductor structure, and more particularly, to a method of forming a semiconductor structure in which a memory unit is integrated with a peripheral logic device, a resistor, or a capacitor.
2. Background of the Invention
Data may be repeatedly written into, read from, and erased from non-volatile memory devices, and the data stored in the non-volatile memory devices may be retained even after power supplies of the devices are cut off. Therefore, the non-volatile memory devices have been extensively applied to personal computers and electronic equipment.
An erasable programmable read-only memory with tunnel oxide (i.e., EPROM with tunnel oxide, ETOX) is one of the common memory cell structures. In the ETOX, a floating gate and a control gate for performing erasing/writing operations are made of doped polysilicon. During the ETOX operation, in order to prevent the problem of data error due to over-erasing/writing phenomenon, a select transistor is serially connected at one side of the memory cell to form a two-transistor (2T) structure. When multiple-time programming (MTP) is performed, the programming and reading operations of the memory cell can be controlled by the select transistor.
With the development of a multi-functional chip, a memory unit in a cell area as well as a logic device, a resistor, or a capacitor in a periphery area may be formed on the same chip. However, the process of manufacturing the memory unit is often separated from the process of manufacturing the peripheral device; hence, several photo masks may be required, and the manufacturing processes are rather complicated. This may increase the manufacturing costs and weaken the competitiveness.